High linearity low noise variable gain amplifier with continuous gain control

ABSTRACT

A variable gain amplifier comprises a plurality of serially connected transistor cells, in which each of the transistor cells has a plurality of connecting terminals. The first terminals of the transistor cells are serially coupled together to receive a first input voltage. The second terminals of the transistor cells are serially connected via a first set of resistors between adjacent cells and coupled to a first gain control. Each of the second terminals is AC or virtual grounded. The third terminals of the transistor cells are coupled together to supply a positive current output. The fourth terminals of the transistor cells are coupled together to supply a negative current output.

TECHNICAL FIELD

The subject matter presented herein relates to a variable gainamplifier, and more particularly to an improved variable gain amplifierthat provides high linearity, low noise performance at a wider frequencybandwidth with continuous gain control.

BACKGROUND

A variable gain amplifier (VGA) is used in a wide range of communicationsystems. Due to its frequent use in a variety of situations, it isdesirable for a VGA to have features in order to maintain a good dynamicrange across a full gain control range. For example, desirablecharacteristics of a VGA include high linearity, low noise, low DC powerconsumption, linear-in-dB gain control, high frequency operation, andgain setting independent of temperature.

FIG. 1 (Prior Art) illustrates a conventional multi-stage VGA 100. TheVGA 100 receives inputs +Vin/2 and −Vin/2 and provides outputs Iout+ andIout−. The inputs are applied to the bases of transistors 10 and 36,respectively, which have their emitters coupled to ground throughrespective current sources. Connected in series between transistor 10and ground are resistors 24-34 and a current gain control (GC) 24.Connected in series between transistor 36 and ground are resistors 48-58and a different current gain control 72.

Connected between Iout+ and Iout− are six differential pairs oftransistors. The emitters of a first differential pair of transistors 10and 46 are connected together. The emitters of a second differentialpair of transistors 12 and 44 are connected together. The emitters of athird differential pair of transistors 14 and 42 are connected together.The emitters of a fourth differential pair of transistors 16 and 40 areconnected together. The emitters of a fifth differential pair oftransistors 18 and 38 are connected together. The emitters of a sixthdifferential pair of transistors 20 and 36 are connected together. Eachof the transistor emitters has a tail current source. For example, thefirst differential pair has a tail current source 60. The seconddifferential pair has a tail current source 62. The third differentialpair has a tail current source 64. The fourth differential pair has atail current source 66. The fifth differential pair has a tail currentsource 68. The sixth differential pair has a tail current source 70.

The base of transistor 12 is connected to the junction between resistors24 and 26. The base of transistor 14 is connected to the junctionbetween resistors 26 and 28. The base of transistor 16 is connected tothe junction between resistors 28 and 30. The base of transistor 18 isconnected to the junction between resistors 30 and 32. The base oftransistor 20 is connected to the junction between resistors 32 and 34.The base of transistor 38 is connected to the junction between resistors48 and 50. The base of transistor 40 is connected to the junctionbetween resistors 50 and 52. The base of transistor 42 is connected tothe junction between resistors 52 and 54. The base of transistor 44 isconnected to the junction between resistors 54 and 56. The base oftransistor 46 is connected to the junction between resistors 56 and 58.

Input voltages +Vin/2 and −Vin/2 are delivered to the bases of thetransistors 10-46 in different versions that are shifted in accordancewith the voltage drops across resistors 24-58. If the resistances of allresistors are equal (R), an offset voltage exists between the bases ofeach differential pair of transistors. The offset for the first pair isequal to the difference between the input voltage at the base oftransistor 10 and the voltage drops across the five resistors 48 through56, or proportional to 5×R. The offsets for the second through sixthpairs are proportional to 3×R, R, R, 3×R and 5×R, respectively. Theoffset for each pair is designated to be R_(i,) wherein i represents thenumber of the differential pairs.

With zero gain control currents in the resistor paths, all differentialpairs operate without any offset and maximum gain is obtained.Increasing the gain control current will produce different offsetsacross the individual pairs, thereby downwardly adjusting the gain. Thegain with respect to control current is represented by the followingrelationship:

$\begin{matrix}{{{I_{out}\left( V_{i\; n} \right)} = {\alpha_{F}*I_{ptat}*{\sum\limits_{i = 1}^{n}{\tanh \frac{V_{i\; n} - \phi_{i}}{2V_{T}}}}}}{{{\phi_{i}/\left( {R \cdot {GC}} \right)} = {n - 1}},{n - 3},\ldots \mspace{11mu},{- \left( {n - 3} \right)},{- \left( {n - 1} \right)}}{{{{for}\mspace{14mu} i} = 1},2,\ldots \mspace{11mu},{n - 1},n}} & (1)\end{matrix}$

Where I_(ptat) is the differential pair tail current, α_(F) is the ratiobetween the collector and emitter current of the correspondingtransistors, V_(T) is the thermal voltage, and Ψ_(i) is the DC offset ofthe differential pair i. The transconductance can be derived bydifferentiating I_(out) with respect to V_(in).

$\begin{matrix}{{{gm}\left( V_{i\; n} \right)} = {\frac{\alpha_{F}*I_{ptat}}{2V_{T}}*{\sum\limits_{i = 1}^{n}{{sech}^{2}\frac{V_{i\; n} - \phi_{i}}{2V_{T}}}}}} & (2)\end{matrix}$

FIG. 2 shows plots of transconductance of VGA 100 with respect to theinput voltage, wherein the X axis represents the input voltage and the Yaxis represents gm. Different curves 205, 210, 215, 220, 225, and 230correspond to gm measured with respect to different gain controlcurrents (GCs). The most sharp curve corresponds GC=0. The curve markedwith a diamond symbol corresponds to GC=60. The curve marked with adownward triangle symbol corresponds to GC=120. The curve marked with aupward triangle symbol corresponds to GC=180. The curve marked with asquare symbol corresponds to GC=240. The curve marked with a “+” symbolcorresponds to GC=300. As the gain control current GC increases, gmdecreases or the gain becomes smaller. In addition, when gm decreases,gm is linear across a wider range of input voltage. That is, thelinearity of the VGA 100 improves as the gain is lower.

In the VGA 100, the resistors 24-58 present along the signal path maysignificantly degrade the VGA's performance. For example, the bandwidthand the high frequency operation of the VGA may be negatively affected.In addition, the presence of these resistors may degrade the noiseperformance of the VGA 100. Even though the bandwidth of the VGA 100 maybe compensated by employing a low resistance and a high GC current, thehigh degree of noise caused by the high GC current may degrade the VGA'sperformance. Furthermore, the high GC current also increases the DCpower consumption, which is undesirable. This is shown in FIG. 3 a,which shows the VGA's gain and its input referred noise with respect tofrequency under different control currents. In FIG. 3 a, the X axisrepresents frequency. The Y axis of the upper portion of FIG. 3 arepresents the amplitude of the noise. The Y axis of the lower portionof FIG. 3 a represents the amount of gain measured. Different curves ineach plot correspond to different gain control current. The top curvemarked with a square symbol corresponds GC=0. The curve marked with adiamond symbol corresponds to GC=60. The curve marked with a downwardtriangle symbol corresponds to GC=120. The curve marked with a upwardtriangle symbol corresponds to GC=180. The curve marked with a squaresymbol corresponds to GC=240. The curve marked with a “+” symbolcorresponds to GC=300. As can be seen, when the control current ishigher, the VGA's gain decreases. When the frequency increases, theVGA's gain also decreases.

In addition, the VGA's performance is also affected by temperature. Asevident from equation (2), transconductance is a function of thermalvoltage V_(T), which varies with temperature. V_(T) is an element in thedenominator of two parts of the gain equation. Thus, in the knownamplifier gain stage of FIG. 1, gain is variable with temperature. FIG.3 b shows plots of linearity-in-dB and gain with respect to gain controlcurrent GC. The linearity error and the gain are relatively linear inthe central range, of approximately 0.4 m to 0.6 m, while having anincreasing error in linearity through the range above 0.6 m. The plot oflinearity-in-dB exhibits curvature, the extent of which can beappreciated in FIG. 3 b. To have a VGA that maintains quality highfrequency operation, high linearity, low DC power consumption,linear-in-dB gain control, and robust performance against noise, andgain setting independent of temperature, an improved VGA is needed.

SUMMARY

The present teaching describes a variable gain amplifier. The variablegain amplifier described herein comprises a plurality of seriallyconnected transistor cells, each of which has a plurality of connectingterminals, through which the transistors are connected. First terminalsof the transistor cells are serially coupled together to receive aninput voltage. Second terminals of the transistor cells are seriallyconnected via a set of resistors positioned between adjacent transistorcells and coupled together to a gain control. Each of the secondterminals is coupled to an AC ground or a virtual ground. Thirdterminals of the transistor cells are coupled together and to a positivecurrent output node. Fourth terminals of the transistor cells arecoupled together and to a negative current output node.

In accordance with another aspect, the variable gain amplifier comprisesa plurality of serially connected transistor cells and a dynamic basecurrent compensation unit, that has a plurality of components, each ofwhich corresponds to a respective one of the transistor cells. Theserially connected transistor cells receive an input voltage and arecoupled to a gain control, a positive current output node, and anegative current output node. Each of the transistors is coupled to acorresponding component in the dynamic base current compensation unit toreceive a dynamically compensated base current.

BRIEF DESCRIPTION OF THE DRAWINGS

The inventions claimed and/or described herein are further described interms of exemplary embodiments. These exemplary embodiments aredescribed in detail with reference to the drawings. These embodimentsare non-limiting exemplary embodiments, in which like reference numeralsrepresent similar structures throughout the several views of thedrawings, and wherein:

FIG. 1 (Prior Art) depicts a circuit for a variable gain amplifier;

FIG. 2 (Prior Art) shows plots of transconductance of a VGA with respectto an input voltage under different gain control current;

FIG. 3 a (Prior Art) shows plots of a VGA's gain with respect tofrequency under different noise conditions;

FIG. 3 b (Prior Art) shows plots of linearity-in-dB and gain of a VGAwith respect to gain control current;

FIG. 4 a depicts an exemplary circuit using a pair of transistors toform a quasi differential pair, according to an embodiment of thepresent invention;

FIG. 4 a depicts a different circuit using a pair of transistors to forma quasi differential pair, according to an different embodiment of thepresent teaching;

FIG. 4 c depicts a multi-stage VGA according to an embodiment of thepresent teaching;

FIG. 5 a depicts an exemplary circuit using a pair of transistors toform a quasi differential pair, according to an embodiment of thepresent teaching;

FIG. 5 b depicts an exemplary connection made between two quasidifferential pairs of transistors to form a VGA cell, according to anembodiment of the present teaching;

FIG. 5 c depicts an exemplary circuit using two quasi differential pairsof transistors to form a VGA cell, according to an embodiment of thepresent teaching;

FIG. 5 d depicts a multi-stage VGA constructed according to anembodiment of the present teaching;

FIG. 6 illustrates improvement of transconductance of a multi-stage VGA,constructed according to an embodiment of the present teaching, withrespect to an input voltage under different gain control currents;

FIG. 7 illustrates improvement of gain of a multi-stage VGA, constructedaccording to an embodiment of the present teaching, with respect tofrequency under different noise conditions; 100261 FIG. 8 illustratesthe impact of finite beta on transconductance of a multi-stage VGA,constructed according to an embodiment of the present teaching;

FIG. 9 depicts an exemplary circuit implementation of a multi-stage VGAwith dynamic base current compensation, according to an embodiment ofthe present teaching;

FIG. 10 depicts an exemplary circuit implementation of a multi-stage VGAwith dynamic base current compensation, according to a differentembodiment of the present teaching;

FIG. 11 depicts an exemplary circuit implementation that performs gaincontrol current compensation in proportion of absolute temperature toachieve temperature independence of VGA gain;

FIG. 12 depicts an alternative circuit implementation that performs gaincontrol current compensation in proportion to absolute temperature toachieve temperature independence of the VGA gain; and

FIG. 13 shows improvement of linearity-in-dB of VGA with respect to gaincontrol current with gain control current compensation.

DETAILED DESCRIPTION

The present teaching describes different exemplary VGA circuits thateliminate base transistors along a signal path to improve the VGAs'performance with respect to bandwidth, input noise, etc. FIG. 4 adepicts an exemplary circuit of a building block that uses a pair oftransistors 403 and 404 having their emitters coupled together to form aquasi differential pair 400, according to an embodiment of the presentinvention. The base of transistor 403 is connected to an input voltageVin (401) and the base of transistor 404 is AC grounded (407) andcoupled to a gain control. The coupled emitters are connected to ground(402-a) via a current source (402). The collector of transistor 403 isconnected to output current Iout+ (405). The collector of transistor 404is connected to a differential output Iout− (406). FIG. 4 b depicts aquasi differential pair 410 having all the same components as in thetransistor pair 400 except an additional capacitor 408 and a resistor409 to provide AC ground 407 at the base of transistor 404.

FIG. 4 c depicts an embodiment of a multi-stage VGA 415 according to anembodiment of the present teaching. The exemplary circuit of themulti-stage VGA 415 has an input voltage Vin 415-a and provides outputsIout+ (415-b) and Iout− (415-c). Internally, the multi-stage VGA 415comprises 3 stages, corresponding to 420, 430, and 440. Each of thestages is implemented using a quasi differential pair as described inFIG. 4 a or FIG. 4 b. At the first stage (420), a quasi differentialpair of transistors 420-a and 420-b having their emitters coupledtogether connects to a current source 420-d. The collector of transistor420-a is connected to Iout+ (415-b) and the collector of transistor420-b is connected to Iout− (415-c). The base of transistor 420-a isconnected to the input voltage Vin (415-a). A capacitor 420-c and a baseresistor 470 are coupled to the base of transistor 420-b to implement ACground. The resistor 470 is also placed to introduce DC offset. Atcertain frequencies of interest, it can be assumed that the baseresistor 470 is small enough or the capacitor 420-c is large enough sothat they are AC grounded. The base of transistor 420-b is alsoconnected to a gain control 480 via resistors 450 and 460 along thesignal path.

At the second stage (430), a quasi differential pair of transistors430-a and 430-b having their emitters coupled together connects to acurrent source 430-d. The collector of transistor 430-a is connected toIout+ (415-b) and the collector of transistor 430-b is connected to thedifferential output Iout− (415-c). The base of transistor 430-a isdirectly connected, in series, to the base of transistor 420-a of thefirst pair 420 and to the input voltage 415-a. A capacitor 430-c iscoupled to the base of transistor 430-b to provide AC ground. The baseof transistor 430-b is also connected, in series, to the base oftransistor 420-b via a resistor 450 along the signal path.

At the third stage (440), a quasi differential pair of transistors 440-aand 440-b having their emitters coupled together connects to a currentsource 440-d. The collector of transistor 440-a is connected to Iout+(415-b) and the collector of transistor 440-b is connected to thedifferential output Iout− (415-c). The base of transistor 440-a isdirectly connected, in series, to the base of transistor 430-a of thesecond pair 430, the base of transistor 420-a of the first pair 420, andto the input 415-a. A capacitor 440-c is coupled to the base oftransistor 440-b to provide AC ground. The base of transistor 440-b isalso connected, in series, to the base of transistor 430-b via aresistor 460 and to the base of transistor 420-b via resistor 450. Theresistors 450 and 460 introduce DC offsets and do not contribute to ACperformance. In some embodiments, the resistors 456 and 460 are of equalresistance.

In FIG. 4 c, since there is no base resistor in the signal path formedby transistors 420-a, 430-a, and 440-a, the frequency and noiseperformance of VGA 415 is improved. This can be illustrated through theexpression of gain with respect to control current:

$\begin{matrix}{{{I_{out}\left( V_{i\; n} \right)} = {\alpha_{F}*I_{ptat}*{\sum\limits_{i = 1}^{n}{\tanh \frac{V_{i\; n} - \phi_{i}}{2V_{T}}}}}}{{{\phi_{i}/\left( {R*{GC}} \right)} = 1},3,\ldots \mspace{11mu},{{2k} - 1}}{{{{for}\mspace{14mu} i} = 1},2,\ldots \mspace{11mu},k}} & (3)\end{matrix}$

where I_(ptat) is the tail current of an emitter-coupled pair (420-d,430-d, or 440-d). The transconductance of the VGA 415 can be derived bydifferentiating Iout with respect to V_(in) as follows:

$\begin{matrix}{{{gm}\left( V_{i\; n} \right)} = {\frac{\alpha_{F}*I_{ptat}}{2V_{T}}*{\sum\limits_{i = 1}^{k}{{sech}^{2}\frac{V_{i\; n} - \phi_{i}}{2V_{T}}}}}} & (4)\end{matrix}$

The AC operation of the circuit is described below. Using a single pair(e.g., first pair 420) as an example, when the current source 420-d hasinfinite impedance, the input voltage Vin (415-a) is divided equallyacross the base-emitter-junctions of 420-a and 420-b. That is, in/2 isapplied to the base-emitter junction of 420-a and Vin/2 is applied tothe base-emitter junction of 420-b. In this case, the output currents atcollectors of 420-a and 420-b are fully differential and, as a result,the even-order distortion products are cancelled out.

However, in some operating conditions, such a pair may not function as afully differential pair. For example, at a high operating frequency, acurrent source may not have infinite impedance. In this case, signal mayleak into the finite impedance at the coupled emitters of 420-a and420-b. Consequently, the input voltage Vin may not be evenly dividedacross the base-emitter junctions of 420-a and 420-b. The base-emitterjunction of 420-a receives a larger input signal than the emitter-basejunction of 420-b. Under such conditions, the output collector currentsof 420-a and 420-b is not fully differential and, hence, even-orderdistortions are only partially cancelled out. This impact at a highfrequency occurs because a pair of transistors, as depicted in FIG. 4 aor FIG. 4 b, is constructed not as a fully differential pair and can beimproved by modifying the circuit of a cell as described below.

FIG. 5 a depicts a different exemplary pair 500 of emitter-coupledtransistors, according to an embodiment of the present teaching. Thepair 500 comprises a first transistor 502, a second transistor 503, anda current source 507. The emitters of both transistors are coupledtogether to connect to ground via the current source 507. The base oftransistor 502 is connected to an input voltage −Vin/2 (501) and thebase of transistor 503 is connected to AC ground and a gain control(506). The collector of transistor 503 is connected to Iout+ (504) andthe collector of transistor 502 is connected to a differential outputIout− (505).

FIG. 5 b illustrates an exemplary stage 508 of a VGA, constructed bycoupling a first transistor pair 400 and a second transistor pair 500,according to an embodiment of the present teaching. In this illustratedembodiment, the transistor pair 400 is constructed according to FIG. 4 aor FIG. 4 b and the transistor pair 500 is constructed according to FIG.5 a. The ground terminal 402-a in FIG. 4 a and the ground terminal 507-ain FIG. 5 a are coupled together to connect to the ground. The inputterminal 401 of pair 400, or the base of transistor 403, is connected toan input voltage +Vin/2. The input terminal 501 of pair 500, or the baseof transistor 502, is connected to an input voltage −Vin/2. The Iout+terminal (405) of pair 400 is coupled with the Iout+ terminal (504) ofpair 500 and the Iout− terminal (406) of pair 400 is coupled with theIout− terminal (505) of pair 500. The base of transistor 404 (406) ofpair 400 is serially connected to base of transistor 503 of pair 500.FIG. 5 c shows the detailed circuit of VGA 508, according to anembodiment of the present teaching. Each of the pairs has its owncurrent source (402 and 507).

FIG. 5 d depicts an exemplary 3-stage VGA 515 with each stage beingconstructed using the VGA cell 508 as described in FIG. 5 c, accordingto an embodiment of the present teaching. There are three stages of VGAcells, 510, 530, and 544, that are connected in series with a resistor526 between 510 and 530 and a resistor 542 between 530 and 544. In thisexemplary circuit, the base terminal of transistor (512) in cell 5 10connecting to a positive input voltage +Vin/2 is coupled directly, inseries, to the base terminal of transistor 528 in cell 530 and the baseterminal of transistor 546 in cell 544. The base terminal of transistor514 in cell 510 connecting to a negative input voltage −Vin/2 isdirectly coupled, in series, to the base terminal of transistor 532 incell 530 and the base terminal of transistor 548 of cell 544. In eachcell, there are two base-coupled transistors, i.e., transistors 516 and518 in cell 510, transistors 534 and 536 in cell 530, and transistors550 and 552 in cell 544. These base-coupled transistors are alsoconnected in series to a gain control 558 via resistors 524, 526 and542, which introduce DC offsets between the bases of connected cells.

Internally, each cell of VGA 515 comprises two pairs of transistors andtwo current sources connected to the coupled emitters of thetransistors. For example, cell 510 includes a first pair of transistors512 and 516, a second pair of transistors 514 and 518, and two separatecurrent sources 520 and 522. Each pair of transistors is amemitter-coupled pair with the coupled emitters connecting to acorresponding current source. The coupled emitters of 512 and 516 areconnected to ground via current source 520 and the coupled emitters of514 and 518 are connected to ground via current source 522. In apreferred embodiment, both current sources have the same tail currents.

Cells 530 and 544 are similarly constructed. Cells 530 comprises twoemitter-coupled transistor pairs, 528-534 and 532-536, and separatecurrent sources 538 and 540, connecting to the two pairs, respectively.Cells 544 comprises two emitter-coupled transistor pairs, 546-550 and548-552, and separate current sources 554 and 556, connecting to thecorresponding transistor pairs. The common base of transistors 516 and518 are also connecting to resistor 524 for providing AC ground. In someembodiments, when the resistance of resistor 524 is R, the resistance ofboth resistors 526 and 542 are 2*R.

In operation, each stage of VGA 515 functions as a fully differentialpair. This can be seen as follows. The output transfer function can bewritten with respect to an input voltage as follows:

Iout (Vin)=a ₁ *V _(in) +a ₂ *V _(in) ² +a _(in) ³ *V _(in) ³ +a ₄ * V_(in) ⁴+ higher order terms   (5)

Based on the differential topology as depicted in FIG. 5 d, the outputcurrents, Iout+ and Iout−, associated with the positive input +Vin/2 andthe negative input −Vin/2, can be respectively written as follows:

Iout (+V _(in)/2)=a ₁ *V _(in)/2+a ₂*(V _(in)/2)² +a ₃*(V _(in)/2)³ +a₄*(V _(in)/2)⁴+ higher order   (6)

Iout (−V _(in)/2)=−a ₁ *V _(in)/2+a ₂*(−V _(in)/2)² −a ₃*(V _(in)/2)³ +a₄*(−V _(in)/2)⁴+ higher order   (7)

Combining (6) and (7), the total output current is expressed as:

Iout(V _(in))=Iout(+V _(in)/2)−Iout(−V _(in)/2)=2*a ₁ *V _(in)/2+2*a₃*(V _(in)/2)³+ higher odd order   (9)

As can be seen, the even order distortions are effectively eliminated.The output current with respect to a control current can be written asfollows:

$\begin{matrix}{{{I_{out}\left( V_{i\; n} \right)} = {2*\alpha_{F}*I_{ptat}*{\sum\limits_{i = 1}^{k}{\tanh \frac{V_{i\; n} - \phi_{i}}{4V_{T}}}}}}{{{\phi_{i}/\left( {R*{GC}} \right)} = 1},3,\ldots \mspace{11mu},{{2k} - 1}}{{{{for}\mspace{14mu} i} = 1},2,\ldots \mspace{11mu},k}} & (10)\end{matrix}$

where I_(ptat) is the tail current of an emitter-coupled pair. Thetransconductance of VGA 515 can be derived by differentiating I_(out)with respect to V_(in). That is,

$\begin{matrix}{{{gm}\left( V_{i\; n} \right)} = {\frac{\alpha_{F}*I_{ptat}}{2V_{T}}*{\sum\limits_{i = 1}^{k}{{sech}^{2}\frac{V_{i\; n} - \phi_{i}}{4V_{T}}}}}} & (11)\end{matrix}$

FIG. 6 shows simulation results on transconductance of the multi-stageVGA 515. The plots represent transconductance of VGA 515 with respect toinput voltage under different gain control currents. The X axisrepresents the input voltage and the Y axis represents thetransconductance. The most sharp curve corresponds GC=0. The curvemarked with a diamond symbol corresponds to GC=120. The curve markedwith a downward triangle symbol corresponds to GC=240. The curve markedwith a upward triangle symbol corresponds to GC=360. The curve markedwith a square symbol corresponds to GC=480. The curve marked with a “+”symbol corresponds to GC=600.

Each plot corresponds to a different gain control setting. Compared withthe plots in FIG. 2, which shows the frequency response and noiseperformance of a conventional VGA with respect to the same operationalparameters (e.g., gain control range, input voltage range, etc.), theVGA 515 maintains a linear performance over a wider range of inputvoltage across all gain control settings. Since the bases of the commonbase transistors in VGA 515, i.e., transistors 516 and 518 in cell 510,transistors 534 and 536 in cell 530, and transistors 550 and 552 in cell544, are AC grounded, resistors 524, 526, and 542 do not contribute tonoise. Those resistors are not in the signal path so that the frequencyresponse is improved. The gain control current GC does not contribute tonoise either.

FIG. 7 shows plots of the gain of the VGA 515 with respect to frequencyunder different noise conditions. The X axis and the Y axis in FIG. 7represent the same measures as in FIG. 3 a. Different curves in bothplots also correspond to the same GC settings as in FIG. 3 a. Comparedwith the plots shown in FIG. 3 a, both the VGA's (515) frequencyresponse and performance under noise condition are improved.

In situations where the GC current 558 is reduced for low powerconsumption, to maintain the same level of DC offsets, the resistancesof resistors 524, 526, and 542 may can be adjusted proportionally. Inaddition, a change in base currents of the common base transistors(e.g., 516 and 518 in cell 510, 534 and 536 in cell 530, and 550 and 552in cell 544) due to finite beta of the transistors may also causeadditional undesirable impact on DC offsets. An increased DC offset mayreduce the contribution to the VGA's transconductance (i.e., gm) fromthe corresponding cell. A decrease in DC offset may increase thecontribution of the corresponding cell to the VGA's transconductance.FIG. 8 visualizes the impact of finite beta on the transconductance ofVGA 515. The X axis and the Y axis in FIG. 8 represent the same measuresas in FIG. 6. Different plots in FIG. 8 correspond to different gaincontrol currents, each with the same gain control settings as thecorresponding curve shown in FIG. 6. As seen in FIG. 8, the linearity ofthe transconductance of VGA 515 degrades when DC offsets can not bemaintained at the same level.

The negative impact of a finite beta can be compensated to enhance thelinearity of VGA 515. FIG. 9 depicts an exemplary circuit of an improvedmulti-stage VGA 900 with dynamic base current compensation, according toan embodiment of the present teaching. The improved VGA 900 comprises amulti-stage VGA 920 and a dynamic base current compensation unit 910.The multi-stage VGA 920 is shown as an exemplary three-stage VGA, e.g.,constructed, e.g., according to the present teaching as described inFIG. 5 d. Transistors 924, 926, 928 and 932 form a first cell at thefirst stage, transistors 940, 942, 946, and 948 form a second cell atthe second stage, and transistors 956, 958, 960, and 964 form a thirdcell at the third stage. Each of the three cells has a base currentflowing into two base coupled transistors from two different sources.One source originates from a gain control (GC) 970 and the otheroriginates from the dynamic base current compensation unit 910. Forexample, the base current flowing into the two base-coupled transistors928 and 932 of the first cell comprises a current originating from GC970 and a dynamically compensated base current 936. The base currentflowing into the two base-coupled transistors 946 and 948 of the secondcell comprises a current originating from GC 970 and a dynamicallycompensated base current 952. The base current flowing into the twobase-coupled transistors 960 and 964 of the third cell comprises acurrent originating from GC 970 and a dynamically compensated basecurrent 968.

The dynamic base current compensation unit 910 comprises two sub-units.The first sub-unit comprises resistors 915, 905, and 901, transistors903, 907, and 910, GC 912, and current sources 902, 906, and 909. The GC912 operates at the same setting as GC 970 and the resistors 901, 905,and 915 have the same resistance as that of resistors 922, 938, and 954so that the base voltages at the bases of transistors 910, 907, and 903replicate the base voltages at the bases of transistors 964, 948, and932. The second sub-unit of 910 comprises transistors 904, 908, and 911,each of which is responsible for generating a dynamical base currentflowing into the base terminal of two base-coupled transistors in acorresponding cell of VGA 920. For example, the dynamically controlledcurrent 936 flows from the collector of transistor 904 to the commonbase of transistors 932 and 928. The dynamically controlled current 952flows from the collector of 908 into the common base of transistors 948and 946. The dynamically controlled current 968 flows from the collectorof 911 into the common base of transistors 964 and 960.

In operation, the base currents of base-coupled transistors may varydepending upon the gain control setting. To produce a desirable DCoffset (as described in Equation 10) for all gain control settings, itis preferred to ensure that the same amount of gain control currentflowing through resistors 922, 938, and 954. For example, the basecurrent to the first cell comprising transistors 924-932 is2*Iptat/beta, where beta is the current gain of the transistors 924-932and Iptat is the current of each of the current sources 930 and 934.Similarly, the total base current to each of the second cell and thethird cell, respectively, is also 2*Iptat/beta (assuming that alltransistors have the same beta value). Base current may vary with thegain control setting. When this occurs, the actual control currentflowing through resistor 922 is gain control minus base currents of 964,960, 948, 946, 932, and 928. The actual control current flowing throughresistor 938 is gain control minus base currents of 964, 960, 948, and946. The actual control current flowing into resistor 954 is the amountof gain control minus the base currents of 960 and 964. In thissituation, the linearity of transconductance cannot be maintained (asshown in FIG. 8) without base current compensation.

With the dynamic base current compensation unit 910, the subtracted basecurrent in each cell can be adaptively compensated to ensure that theamount of current flowing through the transistors 922, 938, and 954remain the same, yielding the same level of DC offset. In operation, thedifferential pair 903 and 904 is used to produce a compensation current936 in exactly the same amount as the total base currents of transistors928 and 932. This can be achieved by the shown circuit because the firstsub-unit of 901, as described above, replicates the common base voltageof transistors 928 and 932. That is , the base voltage of 903 equals thebase voltage of 928 and 932 and the base voltage of 907 equals that of946 and 948. In addition, the current source 902 is designed to have atail current (2*Iptat/beta) that enables 910 to keep track of beta andIptat parameters of VGA 920. When GC increases (i.e., both 970 and 912increase the same way), the base voltage at the base of transistor 932(and 928) increases to Vcm+GC*R, where R is the resistance of resistor922. So is the base voltage of 903. Due to the increase in the inputvoltage at the base of transistor 932, the base current of 932increases, which causes a decrease in the amount of current flowingthrough resistor 922 along the signal path.

To maintain an equal DC offset, the dynamically compensated current,e.g., 936, preferably equals the increase in the base currents of 932and 928. Since the sub-unit of 910 replicates the signal path in VGA920, the input voltage at the base of transistor 903 also increases toVcm+GC*R, which causes a decrease in the base current of transistor 903for the same amount (assuming all transistors have the same beta value)and an increase in current 936 for the same amount. The base currents ofthe other two exemplary cells can be similarly compensated. With thisdynamic base current compensation, the control currents flowing intoresistors 922, 938, and 954 remain the same for all gain settings (as ifwithout subtracting the base currents of 928-932 pair, the 946-948 pair,or the 960-964 pair). By maintaining a desired amount of current flowingthrough the signal path, a desired DC offset can be maintained for allgain settings as well so that a linear transconductance can beaccordingly achieved.

FIG. 10 depicts a different exemplary circuit implementation of animproved multi-stage VGA 1000 with dynamic base current compensation,according to another embodiment of the present teaching. The improvedVGA 1000 similarly comprises a VGA 1040 and a dynamic base currentcompensation unit 1010. In this exemplary VGA 1040, there are threecells (1042-1054, 1060-1072, and 1076-1090), constructed slightlydifferently from what is illustrated in 920. Each cell in 1040 has acapacitor connected to the base of the two base-coupled transistors toprovide AC ground. Capacitor 1052 is coupled with the common base oftransistors 1046 and 1048. Capacitor 1072 is coupled with the commonbase of transistors 1066 and 1068. Capacitor 1090 is coupled with thecommon base of transistors 1082 and 1084. In addition, resistor 1030 isconnected between a positive input voltage +Vin/2 at the base oftransistor 1042 and a voltage reference Vcm and resistor 1032 isconnected between a negative input voltage −Vin/2 and Vcm. In apreferred embodiment, the resistances of these two resistors are at thesame level of resistance and are adequately small so that there is no DCoffset. Resistor 1034 has resistance of R. Resistors 1056 and 1078 havethe same level of resistance of 2*R.

The dynamic base current compensation unit 1010 comprises threesub-units, i.e., 1012-1016, 1018-1022, and 1024-1028, each of whichcorresponds to a VGA cell and is responsible for generating adynamically controlled current for compensating the base current of thecorresponding cell. The first sub-unit of 1012-1016 provides acompensation current 1058 to the common base of the first cell1042-1054. The second sub-unit of 1018-1022 provides a compensationcurrent 1074 to the common base of the second cell 1060-1072. The thirdsub-unit of 1024-1028 provides a compensation current 1088 to the commonbase of the third cell 1076-1090. Each sub-unit includes two transistorsthat are cross-connected. For example, the base of transistor 1014 inthe first sub-unit 1012-1016 is coupled to the collector of transistor1016 and vice versa. In this pair of transistors, the collector of onetransistor, e.g., 1014 has its collector connected to Vcm and the othertransistor, e.g., 1016 has its collector connected to the common base oftwo base-coupled transistors of the corresponding VGA cell, e.g.,transistors 1046 and 1048. The transistors 1014-1016 in the sub-unit arealso emitter-coupled, together connecting to a current source 1012 witha tail current (2*Iptat/beta).

In operation, when gain control 1092 in VGA 1040 changes, the base inputvoltage at the base-coupled transistors in each cell also changes. Forexample, when GC 1092 increases, the input voltage of transistors 1046and 1048 is Vcm+GC′*R, where R is the resistance of resistor 1034. Thishigher voltage at the base of 1046 and 1048 results in a higher basecurrents in transistors 1046 and 1048 so that the control currentflowing into resistor 1034 is GC′ subtracting the base currents of 1046and 1048. GC′ equals to GC minus base currents of 1084, 1082, 1068,1066, 1046, and 1048. To maintain a constant DC offset along the signalpath, it is desirable to compensate this base current change.

As can be seen in FIG. 10, the base voltage of transistor 1014 equalsthe base input voltage of the base-coupled transistors 1046 and 1048.When there is an increase in the base voltage of 1046 and 1048, thecollector current of 1014 decreases in the amount of the base currentchanges with respect to 1046 and 1048. The collector current of 1016increases by the same amount due to the constant current source 1012,i.e., the amount of total base current changes in 1046 and 1048. Suchdynamically generated compensation current is provided as thecompensation current 1058 to the common base of 1046 and 1048 toincrease the current flowing into resistor 1034 to compensate thesubtracted amount. In this way, the DC offsets along the signal pathremains constant even when the gain control 1092 changes. Othersub-units of the base current compensation unit 1010 operate in the sameway.

Although a gain control current, e.g., GC 1092, is generally consideredtemperature independent, it is often affected by temperature, whichmakes an underlying VGA temperature dependent. This is illustrated inequation (4) and (11). Therefore, it is desirable to compensate a gaincontrol current so that it is temperature independent or proportional toan absolute temperature (PTAT). FIG. 11 depicts an exemplary temperaturecompensation circuit designed to perform gain control currentcompensation to improve temperature independence of a VGA. In FIG. 11,I_(ctl) 1115 is a control current source that may be derived from avariable gain control voltage setting and is independent of temperature.Coupled in series between source terminals Vcc and ground arezero-temperature-coefficient DC current sources I_(ztc) 1110 andbase-emitter connected diode 1120. Transistor 1125 is coupled betweenVcc and I_(ztc) 1130. In addition, coupled between Vcc and ground aretransistor 1135 and current source I_(ptat) 1145, which is proportionalto an absolute temperature. The base of transistor 1135 is coupled tothe junction between current source I_(ctl) 1115 and diode 1120.Transistor 1140 is coupled to current source I_(ptat) 1145. The bases oftransistors 1125 and 1140 are coupled to a voltage reference. Transistor1140 produces a current source GC that is coupled to the gain control ofa VGA.

If the base current of transistor 1135 is negligible in comparison tothe other circuit currents, the voltage difference between the basestransistors 1135 and 1140 should closely follow the voltage differencebetween the bases of diode 1120 and transistor 1125. The circuit shownin FIG. 11 linearly converts the temperature-independent gain controlcurrent I_(ctl) to PTAT-dependent current GC with current gainamplification that can be derived as follows:

V _(be1120) −V _(be1125) =V _(be1135) −V _(be1140)

(I _(ztc) −I _(ctl))/I _(ctl)=(I _(ptat) −GC)/GC

GC=I _(ctl) *I _(ptat) /I _(ztc)

Where V_(be1120), V_(be1125), V_(be1135), V_(be1140) are the baseemitter voltages of the associated transistors. The impact of the basecurrent of transistor 1135 has been neglected based on the assumptionthat I_(ptat) is on the order of I_(ztc) or less. Current will vary fromzero to I_(ptat) when the control current I_(ctl) changes from zero toI_(ztc).

When the current gain amplification is large, the base currents oftransistors 1135 and 1140 become significant in comparison to I_(ctl).The base current will be largest when transistor 1135 is set toI_(ptat). FIG. 12 depicts an improved gain control current compensationcircuit designed to reduce the effects of the base currents. In FIG. 12,emitter follower transistors 1262 and 1266 are each coupled to a currentsource between the supply terminals Vcc and ground. The base oftransistor 1262 is coupled to the junction between current sourceI_(ctl) 1252 and diode 1256. The emitter of transistor 1262 is coupledto the base of transistor 1268. The base of transistor 1266 is coupledto the voltage reference. A cross-coupled transistors 1264 and 1268 areplaced in the conduction paths, respectively, of transistors 1262 and1266. Resistor 1270 is coupled in series with transistor 1264. The baseof transistor 1276 is coupled to resistor 1270. The cross-coupledtransistors minimize voltage error, as can be appreciated by thefollowing relationships. The translinear loop voltage relationshipyields the following:

Vb1256−(Vbe1262+Vbe1268+Vb1278)=Vb ₁₂₅₈−(Vbe1266+Vbe1264+Vb1276),

Where “b” represents base voltage and “be” represents base-emittervoltage of the respective transistors. As transistor 1262 conducts thesame collector current as transistor 1264, and transistor 1266 conductsthe same collector current as transistor 1268,

Vbe1262=Vbe1264 and Vbe1266=Vbe1268, and Vb1256−Vb1278=Vb1258−Vb1276 OrVb1256−Vb1258=Vb1278−Vb1276.

The voltage error induced by the emitter followers caused by large basecurrents at transistors 1276 and 1278 is effectively eliminated by thecross-coupled transistors 1264 and 1268.

The circuit in FIG. 12 also corrects for the prior art nonlinear-in-dBgain as a function of GC as exemplified in FIG. 3 b. To compensate forthe error shown in the range above 0.6 m of those plots, more DC currentis needed to pull the gain down for the same control current. Thedesired linear curvature is obtained by insertion of resistor 1270 andits effect in circuit with the base resistances of transistors 1276 and1278. Gain linearity of a VGA with temperature compensated gain controlcurrent is plotted in FIG. 13. As can be seen from the figure, there issubstantially no linearity error from a GC of approximately 0.4 mAthroughout the remaining range.

While the disclosure has been made with reference to the certainillustrated embodiments, the words that have been used herein are wordsof description, rather than words of limitation. Changes may be made,within the purview of the appended claims, without departing from thescope and spirit of the invention in its aspects. Although theinventions have been described herein with reference to particularstructures, acts, and materials, the invention is not to be limited tothe particulars disclosed, but rather can be embodied in a wide varietyof forms, some of which may be quite different from those of thedisclosed embodiments, and extends to all equivalent structures, acts,and, materials, such as are within the scope of the appended claims.

1. A variable gain amplifier, comprising: a plurality of seriallyconnected transistor cells, wherein each of the transistor cells has aplurality of connecting terminals, first terminals of the transistorcells are serially coupled together to receive a first input voltage,second terminals of the transistor cells are serially connected, via afirst set of resistors between adjacent cells, and coupled to a firstgain control, each of the second terminals being coupled to an AC groundor a virtual ground, third terminals of the transistor cells are coupledtogether and to a positive current output node, and fourth terminals ofthe transistor cells are coupled together and to a negative currentoutput node.
 2. The variable gain amplifier of claim 1, wherein thefirst gain control is coupled to one end of the serially connectedsecond terminals.
 3. The variable gain amplifier of claim 1, whereineach of the transistor cells comprises a transistor pair.
 4. Thevariable gain amplifier of claim 3, wherein the transistor pair includesfirst and second transistors having their emitters coupled together andto a current source; the base of the first transistor corresponds to thefirst terminal of the transistor cell; the collector of the firsttransistor corresponds to the third terminal of the transistor cell, thebase of the second transistor corresponds to the second terminal of thetransistor cell; and the collector of the second transistor correspondsto the fourth terminal of the transistor cell.
 5. The variable gainamplifier of claim 4, wherein the current source provides a tail currentof a prescribed amount.
 6. The variable gain amplifier of claim 4,wherein the transistor cell further comprises a capacitor coupled to thebase of the second transistor and ground to provide the AC ground or thevirtual ground to the base of the second transistor.
 7. The variablegain amplifier of claim 1, wherein each of the transistor cellscomprises first and second transistor pairs.
 8. The variable gainamplifier of claim 7, wherein the first transistor pair includes firstand second transistors having their emitters coupled together and to afirst current source; the base of the first transistor corresponds tothe first terminal of the transistor cell; the collector of the firsttransistor corresponds to the third terminal of the transistor cell; thebase of the second transistor corresponds to the second terminal of thetransistor cell; and the collector of the second transistor correspondsto the fourth terminal of the transistor cell.
 9. The variable gainamplifier of claim 8, wherein the second transistor pair includes thirdand fourth transistors having their emitters coupled together and to asecond current source; the base of the third transistor is connected toa second input voltage; the collector of the third transistor isconnected to the collector of the second transistor; the base of thefourth transistor is connected to the base of the second transistor; andthe collector of the fourth transistor is connected to the collector ofthe first transistor.
 10. The variable gain amplifier of claim 9,wherein each of the first and second current sources provides a tailcurrent of a prescribed amount.
 11. The variable gain amplifier of claim9, wherein the first and second current sources provide currents of asame prescribed amount.
 12. The variable gain amplifier of claim 1,further comprising a dynamic base current compensation unit havingterminals coupled with corresponding second terminals and capable ofproviding a compensation current to each of the transistor cells viacorresponding second terminal coupled therewith.
 13. The variable gainamplifier of claim 12, wherein the dynamic base current compensationunit comprises: a plurality of emitter-coupled transistor pairs, each ofthe pairs corresponding to one of the transistor cells; a plurality ofcurrent sources, each corresponding to one of the emitter-coupledtransistor pairs and coupled to the coupled emitters of the pair; and asecond set of resistors corresponding to the first set of resistors andhaving substantially the same resistance, respectively, as that of acorresponding resistor in the first set of resistors, wherein the basesof first transistors of the emitter-coupled transistor pairs areserially connected via the second set of resistors between adjacentfirst transistors, the serially connected bases of the first transistorsis coupled, at one end, to a second gain control that has the samesetting as the first gain control and, at the other end, to a referencevoltage, the collectors of the first transistors of the emitter-coupledtransistor pairs are serially coupled, the bases of second transistorsof the emitter-coupled transistor pairs are serially coupled to an ACground or a virtual ground, and the collectors of second transistors ofthe emitter-coupled transistor pairs are respectively coupled tocorresponding second terminals of the transistor cells.
 14. The variablegain amplifier of claim 13, wherein each of the current sources providesa tail current in an amount that is twice Iptat/beta, where Iptat is atail current provided by an individual current source in each of thetransistor cells and beta characterizes transistors in the transistorcells.
 15. The variable gain amplifier of claim 12, wherein the dynamicbase current compensation unit comprises: a plurality of cross-coupledtransistor pairs, each of the pairs corresponding to one of thetransistor cells; a plurality of current sources, each of whichcorresponding to one of the cross-coupled transistor pairs andconnecting to coupled emitters of the corresponding cross-coupledtransistor pair, wherein collectors of first transistors of thecross-coupled transistor pairs are serially connected to receive avoltage reference, and collectors of second transistors of thecross-coupled transistor pairs are coupled to the second terminals ofcorresponding transistor cells, respectively.
 16. The variable gainamplifier of claim 15, wherein each of the current sources provides atail current in an amount that is twice Iptat/beta, where Iptat is atail current provided by an individual current source in each of thetransistor cells and beta characterizes transistors in the transistorcells.
 17. The variable gain amplifier of claim 1, wherein the firstgain control provides a temperature compensated gain control current.18. A variable gain amplifier, comprising: a plurality of seriallyconnected transistor cells; and a dynamic base current compensation unithaving a plurality of components, each of which corresponds to arespective one of the transistor cells, wherein the serially connectedtransistor cells receive a first input voltage, the transistor cells arecoupled to a first gain control, a positive current output node, and anegative current output node, and each of the transistor cells iscoupled to a corresponding component in the dynamic base currentcompensation unit to receive a dynamically compensated base current. 19.The variable gain amplifier of claim 18, wherein each of the transistorcells has a plurality of connecting terminals, first terminals of thetransistor cells are serially coupled together to receive the firstinput voltage, second terminals of the transistor cells are seriallyconnected, via a first set of resistors between adjacent cells, andcoupled to the first gain control, each of the second terminals beingcoupled to an AC ground or a virtual ground, third terminals of thetransistor cells are coupled together and to the positive current outputnode, and fourth terminals of the transistor cells are coupled togetherand to the negative current output node.
 20. The variable gain amplifierof claim 18, wherein each of the transistor cells comprises a transistorpair.
 21. The variable gain amplifier of claim 19, wherein thetransistor pair includes first and second transistors having theiremitters coupled together and to a current source; the base of the firsttransistor corresponds to the first terminal of the transistor cell; thecollector of the first transistor corresponds to the third terminal ofthe transistor cell; the base of the second transistor corresponds tothe second terminal of the transistor cell; and the collector of thesecond transistor corresponds to the fourth terminal of the transistorcell.
 22. The variable gain amplifier of claim 18, wherein each of thetransistor cells comprises a first transistor pair and a secondtransistor pair.
 23. The variable gain amplifier of claim 22, whereinthe first transistor pair includes first and second transistors havingtheir emitters coupled together and to a first current source, whereinthe base of the first transistor corresponds to the first terminal ofthe transistor cell; the collector of the first transistor correspondsto the third terminal of the transistor cell; the base of the secondtransistor corresponds to the second terminal of the transistor cell,and the collector of the second transistor corresponds to the fourthterminal of the transistor cell; and the second transistor pair includesthird and fourth transistors having their emitters coupled together andto a second current source, wherein the base of the third transistor isconnected to a second input voltage, the collector of the thirdtransistor is connected to the collector of the second transistor, thebase of the fourth transistor is connected to the base of the secondtransistor, and the collector of the fourth transistor is connected tothe collector of the first transistor.
 24. The variable gain amplifierof claim 19, wherein the dynamic base current compensation unitcomprises: a plurality of emitter-coupled transistor pairs, each of thepairs corresponding to one of the transistor cells; a plurality ofcurrent sources, each corresponding to one of the emitter-coupledtransistor pairs and coupled to the coupled emitters of the pair; and asecond set of resistors corresponding to the first set of resistors andhaving substantially the same resistance, respectively, as that of acorresponding resistor in the first set of resistors, wherein the basesof first transistors of the emitter-coupled transistor pairs areserially connected via the second set of resistors between adjacentfirst transistors, the serially connected bases of the first transistorsis coupled, at one end, to a second gain control that has the samesetting as the first gain control and, at the other end, to a referencevoltage, the collectors of the first transistors of the emitter-coupledtransistor pairs are serially coupled, the bases of second transistorsof the emitter-coupled transistor pairs are serially coupled to an ACground or a virtual ground, and the collectors of second transistors ofthe emitter-coupled transistor pairs are respectively coupled tocorresponding second terminals of the transistor cells.
 25. The variablegain amplifier of claim 24, wherein each the current sources provides atail current in an amount that is twice Iptat/beta, where Iptat is atail current provided by an individual current source in each of thetransistor cells and beta characterizes transistors in the transistorcells.
 26. The variable gain amplifier of claim 19, wherein the dynamicbase current compensation unit comprises: a plurality of cross-coupledtransistor pairs, each of the pairs corresponding to one of thetransistor cells; a plurality of current sources, each of whichcorresponding to one of the cross-coupled transistor pairs andconnecting to coupled emitters of the corresponding cross-coupledtransistor pair, wherein collectors of first transistors of thecross-coupled transistor pairs are serially connected to receive avoltage reference, and collectors of second transistors of thecross-coupled transistor pairs are coupled to the second terminals ofcorresponding transistor cells, respectively.
 27. The variable gainamplifier of claim 26, wherein each of the current sources provides atail current in an amount that is twice Iptat/beta, where Iptat is atail current provided by an individual current source in each of thetransistor cells and beta characterizes transistors in the transistorcells.
 28. The variable gain amplifier of claim 18, wherein the firstgain control provides a temperature compensated gain control current.